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Chapter 4

Lab task 2 - Design a JPEG

accelerator

4.1 The lab system

In this lab task you will learn how to build a hardware accelerator for the JPEG image

compression algorithm. In this lab you will use the build target dafk.bit. This is a

complete system with the following components:

• OR1200 CPU

• Boot monitor

• UART

• VGA controller

• Camera controller

• Ethernet controller

• SDRAM, SRAM, and ﬂash memory controller

µClinux is programmed into the ﬂash memory on the FPGA board and we will use

this operating system for the remainder of this course. Examples of how to compile

for Linux are included in the lab skeleton in the hello directory.

4.2 Proposed architecture

We propose the general architecture shown in Figure 4.1. It works in the following

way:

1. An 8 × 8 bytes image is written from the Wishbone bus by the application pro-

gram to the in RAM in 16 write cycles. Pixels are 8-bit positive numbers and

packed in one 32-bit word. We recommend that you s ubtract 128 from each pixel

before it is written to the in RAM. The accelerator is then started by setting the

START bit in csr (Control/Status Register).

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Cypress DCT-1D Guida Utente Pagina 43