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CHAPTER 1. THE SYST EM

The OR1200 CPU, [8], consists of several blocks:

• High Performance 32-Bit CPU/DSP

– 32-bit architecture implementing ORBIS32 instruction set

– Scalar, single-issue 5-stage pipeline delivering sustained throughput

– Single-cycle instruction execution on most instructions

– Can be run at 250MHz in an ASIC

– Thirty-two, 32-bit general-purpose registers

– Custom user instructions

• L1 Caches

– Harvard model with split instruction and data cache

– Instruction/data cache size scalable from 1KB to 64KB

• Memory Management Unit

– Harvard model with split instruction and data MMU

– Instruction/data TLB size scalable from 16 to 256 entries

– Direct-mapped hash-based TLB

– Linear address space with 32-bit virtual address and physical address from

24 to 32 bits

– Page size 8KB with per-page attributes

• Advanced Debug Unit

– Conventional target-debug agent with a debug exception handler

– Non-intrusive debug/trace for both RISC and system

– Access and control of debug unit from RISC or via development interface

• Integrated Tick Timer

– Task scheduling and precise time measuring

– Maximum timer range of 2

clock cycles

– Maskable tick-timer interrupt

• Programmable Interrupt Controller

– 2 non-maskable interrupt sources

– 30 maskable interrupt sources

– two interrupt priorities

In this lab course the Power Management module is disabled.

1.3.4 The Wishbone Interconnect Bus

The Wishbone Interconnect is a standard way of connecting IP (Intellectual Property)

blocks in System-on-Chip designs, see for instance [9]. It can be implemented in

different ways ranging from a fully connected crossbar to an ordinary shared bus. In

this course the shared bus variant is used. It is important to understand that there is no

parallelism in this implementation. It is just a connection between one master and one

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Cypress DCT-1D Guida Utente Pagina 14