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3.2. SOME BASIC FACTS ON THE WISHBONE BUS

3. The Master deasserts the wb.stb, wb.cyc and wb.we-signals.

4. The slave deasserts the wb.ack-signal.

For the read cycle, see Figure 3.2c, we have:

1. The master places the address on the bus wb.adr and asserts the wb.stb-signal,

the wb.cyc-signal, and deasserts the wb.we-signal.

2. The slave, when ready, decodes the address bus, places the data on the data bus

wb.dat_i and asserts the wb.ack-signal.

3. The Master deasserts the wb.stb and wb.cyc-signals.

4. The slave deasserts the wb.ack-signal.

In these basic write and read bus cycles the wb.stb and wb.cyc-signals are identical.

The wb.cyc-signal is used for arbitration of the bus, so the master may assert it for

many cycles, for instance during a cache line reﬁll.

3.2.1 A Wishbone Interconnect

Before we begin with the actual integration of the computer we would like to give a

short explanation of the Wishbone interconnect. In Figur e 3.3 we show an example

of 2 masters and 3 slaves connected to a Wishbone bus. The m-bus is all the signals

going from the master to a slave, like the address bus, data bus and in particular the

stb-signal. The s-bus is all the signals going from the slave to a master, like the data

bus and the ack-signal.

M0 M1

ARB

DEC

S0 S1 S2

m−bus

s−bus

m0 m1

s0 s1 s2

cyc1

M−mux

S−mux

cyc0

Figure 3.3: A Wishbone interconnect for 2 masters and 3 slaves.

An arbiter, a ﬁnite state machine, listens to the cyc-signals from the masters. The

masters M0 and M1 are, in our implementation, granted the bus in a round-robin fash-

ion. The m-bus is then connected to all the slaves. The stb-signal is, however, only

asserted at the addressed slave port.

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Cypress DCT-1D Guida Utente Pagina 31