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1.3. OPEN RISC

Global Clock Mux

DCM DCM IOB

CLB

Programmable I/Os

Block SelectRAM Multiplier

Configurable Logic

Figure 1.3: Virtex-II architectural overview.

1.3 Open RISC

1.3.1 Top Design

The computer used in this lab cours e is designed with Verilog modules, which can

be downloaded free from Open Cores (www.opencores.org) and some modules de-

signed by us.

This section describes the main system deﬁned in the ﬁle dafk.sv, which you will

use in lab task 2–4

The computer in Figure 1.5 consists of the following modules:

• OR1200 CPU:

32 bit RISC CPU with a 5-stage pipeline.

• Wishbone:

An interconnect bus with 16 ports, 8 master ports and 8 slave ports.

• Memory Controller:

A memory controller for SRAM, SDRAM and Flash memories.

• UART:

A 16550 UART with baudrates up to 115200 b/s.

• Ethernet Controller:

An implementation of the MAC layer, which requires an external PHY circuit

for a complete solution.

• Parallel Port

• VGA Controller

• Camera Controller

• DCT Accelerator:

It will be your task to ﬁnish the implementation of this module.

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Cypress DCT-1D Guida Utente Pagina 11