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1.3. OPEN RISC
15
slave. Furthermore tristate is not used, instead there are two databuses, one in each
direction. The address bus and the data busses are 32 bits wide.
A
0
,D
0
A
0
,D
0
A
0
,D
0
,STB
A
7
,D
7
A
1
,D
1
Arbiter
D
1
,ACK
D
1
D
1
D
0
,
D
1
,ACK
D
7
,
Master
Slave
A
0
,D
0
,STB
Address
Decoder
i_bus_m
i_dat_s, i_bus_s
gnt
gnt
A
0
A
7
Figure 1.7: The Wishbone interconnect bus. In this example Master 0 is addressing
Slave 1. Master 0 has won the arbitration.
We will briefly explain how the Wishbone bus works with a simple example. We
assume a computer system like in Figure 1.5 and that the CPU executes a program
in the memory, that is connected to slave port 1, see Figure 1.7. The CPU places an
address A
0
at the address lines at master port 0 and asserts the signal STB. The arbiter
inside the Wishbone grants the bus to master 0. The address A
0
will now show up on
all slave ports. Address decoding logic routes the asserted STB-signal only to slave
port 1. The memory at slave port 1 places D
1
on the data bus and asserts the signal
ACK. D
1
will now show up on all master ports, but ACK will only be asserted at master
port 0.
1.3.5 Memory Controller
In this lab course we will use a simple memory controller, designated PKMC, designed
by us. PKMC is implemented for this particular system and thus needs no configuration.
PKMC handles all communications with the SRAM, SDRAM and FLASH memory.
Especially ensuring that the SDRAM is refreshed correctly.
1.3.6 Ethernet Controller
The Ethernet IP Core, [10], consists of five modules:
• The MAC (Media Access Control) module, for med by transmit, receive, and
control module
• The MII (Media Independent Interface) Management module
• The Host Interface
- Laboratory manual for TSEA44 1
- Contents 3
- CONTENTS 4
- The system 7
- 1.2 Hardware 8
- 1.2. HARDWARE 9
- 1.2.3 Virtex-II 4000 FPGA 10
- 1.3 Open RISC 11
- CHAPTER 1. THE SYST EM 12
- 1.3.3 OR1200 CPU 13
- 1.3.5 Memory Controller 15
- 1.3.6 Ethernet Controller 15
- 1.4 Software 16
- 1.4. SOFTWARE 17
- 1.4.4 µClinux 20
- Lab task 0 - Build a UART in 23
- 2.2.2 The hardware 24
- 2.2.3 A simple testbench 24
- 2.2. A SIMPLE UART 25
- 2.3 Exercises 26
- Preparation task 1 26
- Laboration task 1 26
- 2.4 gtkterm usage 27
- Wishbone bus 29
- Master Slave 30
- 3.2.1 A Wishbone Interconnect 31
- 3.3 A Simple Computer 32
- Preparation task 2 33
- Preparation task 3 34
- Preparation task 4 34
- Laboration task 2 35
- 3.4 A Benchmark Program 36
- 3.4. A BENCHMARK PROGRAM 37
- Preparation task 5 38
- Laboration task 3 39
- 3.6 Useful Commands 40
- 3.7.1 A Note on Volatile 41
- Lab task 2 - Design a JPEG 43
- Preparation task 6 44
- 4.2.2 Distributed RAMs 45
- Preparation task 7 46
- Laboration task 4 47
- Laboration task 5 47
- 4.3 Introduction to µClinux 47
- Laboration task 6 47
- Laboration task 7 48
- 4.4 Introduction to jpegfiles 48
- Preparation task 8 49
- Laboration task 8 50
- Laboration task 9 50
- 4.5 Timestamps 50
- 4.6 Quantization 51
- Preparation task 9 52
- 4.7 Tips and tricks 53
- Lab task 3 55
- WAITREADY 56
- GETBLOCK 56
- WAITREADY_LAST RELEASEBUS 56
- 5.1.2 jpeg_dma.sv 56
- Preparation task 10 58
- Laboration task 10 58
- Laboration task 11 58
- Laboration task 12 58
- CHAPTER 5. LAB TASK 3 60
- Chapter 6 61
- Preparation task 11 62
- Preparation task 12 62
- 6.2 Adding a New Instruction 62
- 6.3 Proposed Architecture 63
- 6.4 Hardware Implementation 64
- 6.5 Software Implementation 65
- Laboration task 13 67
- Laboration task 14 67
- 6.7 Tips and tricks 68
- 6.9 Beyond tsea44 70
- Bibliography 71
- BIBLIOGRAPHY 72
- Open RISC Reference Platform 73
- A.2 Interrupts 74
- The Wishbone specification 75
- B.2 Interface signals 76
- −WSS−CLK_I 77
- B.5 System Verilog Interface 79
- Tips & Trix 81
- APPENDIX C. TIPS & TRIX 82
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