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9-Mbit QDR- II™ SRAM 2-Word

Burst Architecture

CY7C1292DV18

CY7C1294DV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-00350 Rev. *A Revised July 20, 2006

Features

• Separate Independent Read and Write data ports

— Supports concurrent transactions

• 250-MHz clock for high bandwidth

• 2-Word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and

Write ports (data transferred at 500 MHz) @ 250 MHz

• Two input clocks (K and K

) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C

) to minimize

clock-skew and flight-time mismatches

• Echo clocks (CQ and CQ

) simplify data capture in

high-speed systems

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x 18 and x 36 configurations

• Full data coherency, providing most current data

•Core V

= 1.8V (±0.1V); I/O V

DDQ

= 1.4V to V

• Available in 165-ball FBGA package (13 x 15 x 1.4 mm)

• Offered in both lead-free and non-lead free packages

• Variable drive HSTL output buffers

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1292DV18 – 512K x 18

CY7C1294DV18 – 256K x 36

Functional Description

The CY7C1292DV18 and CY7C1294DV18 are 1.8V

Synchronous Pipelined SRAMs, equipped with QDR™-II

architecture. QDR-II architecture consists of two separate

ports to access the memory array. The Read port has

dedicated Data Outputs to support Read operations and the

Write Port has dedicated Data Inputs to support Write opera-

tions. QDR-II architecture has separate data inputs and data

outputs to completely eliminate the need to “turn-around” the

data bus required with common I/O devices. Access to each

port is accomplished through a common address bus. The

Read address is latched on the rising edge of the K clock and

the Write address is latched on the rising edge of the K

clock.

Accesses to the QDR-II Read and Write ports are completely

independent of one another. In order to maximize data

throughput, both Read and Write ports are equipped with

Double Data Rate (DDR) interfaces. Each address location is

associated with two 18-bit words (CY7C1292DV18) or 36-bit

words (CY7C1294DV18) that burst sequentially into or out of

the device. Since data can be transferred into and out of the

device on every rising edge of both input clocks (K and K

and

C and C

), memory bandwidth is maximized while simplifying

system design by eliminating bus “turn-arounds.”

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled

by the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 250 200 167 MHz

Maximum Operating Current 600 550 500 mA

[+] Feedback

1 2 3 4 5 6 ... 22 23

Sommario

Pagina 1 - Burst Architecture

9-Mbit QDR- II™ SRAM 2-WordBurst ArchitectureCY7C1292DV18CY7C1294DV18Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709

Pagina 2

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 10 of 23IDCODEThe IDCODE instruction causes a vendor-specific, 32-bit codeto be loaded int

Pagina 3

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 11 of 23 Note: 9. The 0/1 next to each state represents the value at TMS at the rising edg

Pagina 4

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 12 of 23 TAP Controller Block Diagram0012..293031Boundary Scan RegisterIdentification Reg

Pagina 5

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 13 of 23 TAP AC Switching Characteristics Over the Operating Range[13, 14]Parameter Descr

Pagina 6

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 14 of 23Identification Register DefinitionsInstruction FieldValueDescriptionCY7C1292DV18 C

Pagina 7

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 15 of 23Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID0 6R 27

Pagina 8

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 16 of 23Power-Up Sequence in QDR-II SRAM[16]QDR-II SRAMs must be powered up and initialize

Pagina 9

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 17 of 23Maximum Ratings(Above which the useful life may be impaired.)Storage Temperature

Pagina 10 - CY7C1294DV18

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 18 of 23Note: 22. Unless otherwise noted, test conditions assume signal transition time of

Pagina 11

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 19 of 23 Switching Characteristics Over the Operating Range[22, 23]CypressParameterConsort

Pagina 12 - TAP Controller

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 2 of 23Logic Block Diagram (CY7C1292DV18)CLKA(17:0)Gen.KKControlLogicAddressRegisterD[17:0

Pagina 13

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 20 of 23 Switching Waveforms[27, 28, 29]Read/Write/Deselect SequenceNotes: 27. Q00 refers

Pagina 14

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 21 of 23Ordering InformationNot all of the speed, package and temperature ranges are avail

Pagina 15

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 22 of 23© Cypress Semiconductor Corporation, 2006. The information contained herein is sub

Pagina 16

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 23 of 23Document History PageDocument Title: CY7C1292DV18/CY7C1294DV18 9-Mbit QDR- II™ SRA

Pagina 17

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 3 of 23 Pin Configurations CY7C1292DV18 (512K x 18) 234 5671ABCDEFGHJKLMNPRACQNCNCNCNCDOFF

Pagina 18

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 4 of 23Pin Definitions Pin Name I/O Pin DescriptionD[x:0]Input-SynchronousData input signa

Pagina 19

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 5 of 23Functional OverviewThe CY7C1292DV18 and CY7C1294DV18 are synchronouspipelined Burst

Pagina 20

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 6 of 23Byte Write OperationsByte Write operations are supported by the CY7C1292DV18.A Writ

Pagina 21

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 7 of 23Application Example[1]Truth Table[2, 3, 4, 5, 6, 7] Operation K RPS WPS DQ DQWrite

Pagina 22

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 8 of 23Write Cycle Descriptions (CY7C1294DV18) [2, 8]BWS0BWS1BWS2BWS3KK CommentsL L L L L-

Pagina 23

CY7C1292DV18CY7C1294DV18Document #: 001-00350 Rev. *A Page 9 of 23IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs incorporate a serial boundary sc

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