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CY7C1266V18, CY7C1277V18

CY7C1268V18, CY7C1270V18

36-Mbit DDR-II+ SRAM 2-Word

Burst Architecture (2.5 Cycle Read Latency)

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-06347 Rev. *D Revised March 11, 2008

Features

■ 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36)

■ 300 MHz to 400 MHz clock for high bandwidth

■ 2-Word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 800 MHz) at 400 MHz

■ Read latency of 2.5 clock cycles

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

■ Core V

= 1.8V ± 0.1V; IO V

DDQ

= 1.4V to V

[1]

■ HSTL inputs and variable drive HSTL output buffers

■ Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both in Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.5 cycles:

CY7C1266V18 – 4M x 8

CY7C1277V18 – 4M x 9

CY7C1268V18 – 2M x 18

CY7C1270V18 – 1M x 36

Functional Description

The CY7C1266V18, CY7C1277V18, CY7C1268V18, and

CY7C1270V18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II+ architecture. The DDR-II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K

. Read data is driven on the rising edges

of both K and K

. Each address location is associated with two

8-bit words (CY7C1266V18), 9-bit words (CY7C1277V18),

18-bit words (CY7C1268V18), or 36-bit words (CY7C1270V18),

that burst sequentially into or out of the device.

Asynchronous inputs include output impedance matching input

(ZQ). Synchronous data outputs (Q, sharing the same physical

pins as the data inputs, D) are tightly matched to the two output

echo clocks CQ/CQ

, eliminating the need to capture data

separately from each individual DDR SRAM in the system

design.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the K or K

input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Description 400 MHz 375 MHz 333 MHz 300 MHz Unit

Maximum Operating Frequency 400 375 333 300 MHz

Maximum Operating Current 1280 1210 1080 1000 mA

Note

1. The QDR consortium specification for V

DDQ

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting

DDQ

= 1.4V to V

[+] Feedback [+] Feedback

1 2 3 4 5 6 ... 26 27

Sommario

Pagina 1 - 36-Mbit DDR-II+ SRAM 2-Word

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V1836-Mbit DDR-II+ SRAM 2-WordBurst Architecture (2.5 Cycle Read Latency)Cypress Semiconductor Corporatio

Pagina 2

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 10 of 27Write Cycle Descriptions The write cycle description

Pagina 3

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 11 of 27Write Cycle Descriptions The write cycle description

Pagina 4

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 12 of 27IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs in

Pagina 5

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 13 of 27IDCODEThe IDCODE instruction loads a vendor-specific,

Pagina 6

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 14 of 27TAP Controller State DiagramThe state diagram for the

Pagina 7

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 15 of 27TAP Controller Block DiagramTAP Electrical Characteri

Pagina 8

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 16 of 27TAP AC Switching Characteristics Over the Operating R

Pagina 9

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 17 of 27Identification Register Definitions Instruction Field

Pagina 10 - CY7C1268V18, CY7C1270V18

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 18 of 27Boundary Scan OrderBit # Bump ID Bit # Bump ID Bit #

Pagina 11

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 19 of 27Power Up Sequence in DDR-II+ SRAMDDR-II+ SRAMs must b

Pagina 12

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 2 of 27Logic Block Diagram (CY7C1266V18)Logic Block Diagram (

Pagina 13

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 20 of 27Maximum Ratings Exceeding maximum ratings may impair

Pagina 14

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 21 of 27Capacitance[20]Parameter Description Test Conditions

Pagina 15 - TAP Controller

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 22 of 27Switching Characteristics Over the Operating Range[21

Pagina 16

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 23 of 27Switching WaveformsRead/Write/Deselect Sequence[29, 3

Pagina 17

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 24 of 27Ordering Information Not all of the speed, package an

Pagina 18

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 25 of 27333 CY7C1266V18-333BZC 51-85195 165-ball Fine Pitch B

Pagina 19

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 26 of 27Package DiagramFigure 6. 165-ball FBGA (15 x 17 x 1.4

Pagina 20

Document Number: 001-06347 Rev. *D Revised March 11, 2008 Page 27 of 27All product and company names mentioned in this document are the trademarks of

Pagina 21

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 3 of 27Logic Block Diagram (CY7C1268V18)Logic Block Diagram (

Pagina 22

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 4 of 27Pin ConfigurationsCY7C1266V18 (4M x 8)165-Ball FBGA (1

Pagina 23

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 5 of 27Pin Configurations (continued)CY7C1268V18 (2M x 18)165

Pagina 24

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 6 of 27Pin Definitions Pin Name IO Pin DescriptionDQ[x:0]Inpu

Pagina 25

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 7 of 27ZQ Input Output Impedance Matching Input. This input i

Pagina 26

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 8 of 27Functional OverviewThe CY7C1266V18, CY7C1277V18, CY7C1

Pagina 27

CY7C1266V18, CY7C1277V18CY7C1268V18, CY7C1270V18Document Number: 001-06347 Rev. *D Page 9 of 27Delay Lock Loop (DLL)These chips use a DLL that is des

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