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CY14B108K, CY14B108M
8 Mbit (1024K x 8/512K x 16) nvSRAM with
Real Time Clock
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 001-47378 Rev. *D Revised December 15, 2009
Features
25 ns and 45 ns Access Times
Internally Organized as 1024K x 8 (CY14B108K) or 512K x 16
(CY14B108M)
Hands Off Automatic STORE on Power Down with only a Small
Capacitor
STORE to QuantumTrap Nonvolatile Elements is Initiated by
Software, Device Pin, or AutoStore on Power Down
RECALL to SRAM Initiated by Software or Power Up
High Reliability
Infinite Read, Write, and RECALL Cycles
1 Million STORE Cycles to QuantumTrap
20 year Data Retention
Single 3V +20%, –10% Operation
Data Integrity of Cypress nvSRAM Combined with Full
Featured Real Time Clock (RTC)
Watchdog Timer
Clock Alarm with Programmable Interrupts
Capacitor or Battery Backup for RTC
Industrial Temperature
44 and 54-pin TSOP II Package
Pb-free and RoHS Compliance
Functional Description
The Cypress CY14B108K/CY14B108M combines a 8-Mbit
nonvolatile static RAM with a full featured RTC in a monolithic
integrated circuit. The embedded nonvolatile elements incor-
porate QuantumTrap technology producing the world’s most
reliable nonvolatile memory. The SRAM is read and written
infinite number of times, while independent nonvolatile data
resides in the nonvolatile elements.
The RTC function provides an accurate clock with leap year
tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
STATIC RAM
ARRAY
2048 X 2048 X 2
R
O
W
D
E
C
O
D
E
R
COLUMN I/O
COLUMN DEC
I
N
P
U
T
B
U
F
F
E
R
S
POWER
CONTROL
STORE/RECALL
CONTROL
Quatrum
Trap
2048 X 2048 X 2
STORE
RECALL
V
CC
V
CAP
HSB
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
SOFTWARE
DETECT
A
14
-A
2
OE
CE
WE
BHE
BLE
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
17
A
18
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
RTC
MUX A
19
-A
0
X
out
X
in
INT
V
RTCbat
V
RTCcap
A
19
Logic Block Diagram
[1, 2, 3]
Notes
1. Address A
0
- A
19
for x8 configuration and Address A
0
- A
18
for x16 configuration.
2. Data DQ
0
- DQ
7
for x8 configuration and Data DQ
0
- DQ
15
for x16 configuration.
3. BHE
and BLE are applicable for x16 configuration only.
[+] Feedback
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Sommario

Pagina 1 - Real Time Clock

CY14B108K, CY14B108M8 Mbit (1024K x 8/512K x 16) nvSRAM withReal Time ClockCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134

Pagina 2

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 10 of 31Figure 3. Watchdog Timer Block Diagram.Power MonitorThe CY14B108K provides a power man

Pagina 3

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 11 of 31Figure 4. RTC Recommended Component Configuration Figure 5. Interrupt Block DiagramRe

Pagina 4

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 12 of 31Table 4. RTC Register Map[7]Register BCD Format Data[8]Function/RangeCY14B108K CY14B10

Pagina 5

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 13 of 31Table 5. Register Map DetailRegisterDescriptionCY14B108K CY14B108M0xFFFFF 0x7FFFFTime

Pagina 6

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 14 of 31RegisterDescriptionCY14B108K CY14B108M0xFFFF8 0x7FFF8Calibration/ControlD7 D6 D5 D4 D3

Pagina 7

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 15 of 31RegisterDescriptionCY14B108K CY14B108M0xFFFF4 0x7FFF4Alarm - HoursD7 D6 D5 D4 D3 D2 D1

Pagina 8

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 16 of 31Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice. These

Pagina 9 - Watchdog Timer

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 17 of 31AC Test ConditionsInput Pulse Levels ...

Pagina 10 - CY14B108K, CY14B108M

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 18 of 31RTC Characteristics Parameters Description Min Typ[10]Max UnitsVRTCbatRTC Battery Pin V

Pagina 11

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 19 of 31AC Switching Characteristics ParametersDescription25 ns 45 nsUnitCypressParametersAltPa

Pagina 12

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 2 of 31ContentsFeatures ...

Pagina 13

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 20 of 31Switching WaveformsFigure 8. SRAM Read Cycle 2: CE and OE Controlled[3, 15, 19] Figure

Pagina 14

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 21 of 31Switching WaveformsFigure 10. SRAM Write Cycle 2: CE Controlled[3, 18, 19, 20]Figure 1

Pagina 15

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 22 of 31AutoStore/Power Up RECALLParameters DescriptionCY14B108K/CY14B108MUnitMin MaxtHRECALL [

Pagina 16

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 23 of 31Software Controlled STORE and RECALL Cycle In the following table, the software control

Pagina 17

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 24 of 31Hardware STORE CycleParameters DescriptionCY14B108K/CY14B108MUnitMin MaxtDHSB HSB To Ou

Pagina 18

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 25 of 31Truth Table For SRAM OperationsHSB should remain HIGH for SRAM Operations.For x8 Config

Pagina 19

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 26 of 31Part Numbering NomenclatureOption:T - Tape & ReelBlank - Std.Speed:25 - 25 nsData B

Pagina 20

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 27 of 31Ordering InformationSpeed(ns)Ordering CodePackageDiagramPackage TypeOperatingRange25 CY

Pagina 21

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 28 of 31Package Diagrams Figure 17. 44-Pin TSOP II (51-85087)51-85087 *B[+] Feedback

Pagina 22

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 29 of 31Figure 18. 54-Pin TSOP II (51-85160)Package Diagrams (continued)51-85160 **[+] Feedba

Pagina 23

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 3 of 31 Note4. Address expansion for 16 Mbit. NC pin not connected to die.PinoutsFigure 1. Pin

Pagina 24

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 30 of 31Document History PageDocument Title: CY14B108K, CY14B108M 8 Mbit (1024K x 8/512K x 16)

Pagina 25 - For x16 Configuration

Document #: 001-47378 Rev. *D Revised December 15, 2009 Page 31 of 31All products and company names mentioned in this document are the trademarks of t

Pagina 26

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 4 of 31Device OperationThe CY14B108K/CY14B108M nvSRAM is made up of twofunctional components pa

Pagina 27

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 5 of 31To reduce unnecessary nonvolatile STOREs, AutoStore, andHardware STORE operations are ig

Pagina 28

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 6 of 31Preventing AutoStoreThe AutoStore function is disabled by initiating an AutoStoredisable

Pagina 29

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 7 of 31Data ProtectionThe CY14B108K/CY14B108M protects data from corruptionduring low voltage c

Pagina 30

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 8 of 31Real Time Clock OperationnvTime OperationThe CY14B108K/CY14B108M offers internal registe

Pagina 31 - Products

CY14B108K, CY14B108MDocument #: 001-47378 Rev. *D Page 9 of 31The value of OSCF must be reset to ‘0’ when the time registersare written for the first

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