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1-Mbit (128K x 8) nvSRAM

PRELIMINARY

CY14B101L

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-06400 Rev. *E Revised January 24, 2007

Features

• 25 ns, 35 ns, and 45 ns access times

• “Hands-off” automatic STORE on power down with only a

small capacitor

• STORE to QuantumTrap

nonvolatile elements is initiated

by software, device pin, or Autostore

on power down

• RECALL to SRAM initiated by software or power up

•Infinite READ, WRITE, and RECALL cycles

• 10 mA typical I

at 200 ns cycle time

• 200,000 STORE cycles to quantum trap

• 20-year data retention @ 55°C

• Single 3V operation +20%, –10%

• Commercial and industrial temperature

• SOIC and SSOP packages

• RoHS compliance

Functional Description

The Cypress CY14B101L is a fast static RAM with a

nonvolatile element in each memory cell. The embedded

nonvolatile elements incorporate QuantumTrap technology

producing, the world’s most reliable nonvolatile memory. The

SRAM provides infinite read and write cycles; while

independent, nonvolatile data resides in the highly reliable

QuantumTrap cell. Data transfers from the SRAM to the

nonvolatile elements (the STORE operation) takes place

automatically at power down. On power up, data is restored to

the SRAM (the RECALL operation) from the nonvolatile

memory. Both the STORE and RECALL operations are also

available under software control.

Logic Block Diagram

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

1024 X 1024

QuantumTrap

1024 x 1024

STORE

RECALL

COLUMN IO

COLUMN DEC

ROW DECODER

INPUT BUFFERS

HSB

CAP

[+] Feedback [+] Feedback

1 2 3 4 5 6 ... 18 19

Sommario

Pagina 1 - 1-Mbit (128K x 8) nvSRAM

1-Mbit (128K x 8) nvSRAMPRELIMINARYCY14B101LCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document #:

Pagina 2 - Top View

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 10 of 18AutoStore/Power Up RECALLParameter DescriptionCY14B101LUnitMin MaxtHRECALL [13]Power Up

Pagina 3

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 11 of 18Switching WaveformsSRAM Read Cycle 1(address controlled) [9, 10, 22]SRAM Read Cycle 2 (

Pagina 4 - Hardware RECALL (Power Up)

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 12 of 18SRAM Write Cycle 1(WE controlled) [22, 23]SRAM Write Cycle 2 (CE controlled)Switching W

Pagina 5 - [+] Feedback [+] Feedback

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 13 of 18Figure 3. AutoStore/Power Up RECALLFigure 4. CE-Controlled Software STORE/RECALL Cycle

Pagina 6

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 14 of 18Figure 5. OE-Controlled Software STORE/RECALL Cycle [17]Figure 6. Hardware STORE CycleF

Pagina 7 - DC Electrical Characteristics

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 15 of 18Ordering InformationAll of the following mentioned parts are of “Pb-free” type. Shaded

Pagina 8

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 16 of 18Package DiagramsFigure 8. 32-pin (300-Mil) SOIC, 51-85127PIN 1 IDSEATING PLANE11617 32D

Pagina 9 - AC Switching Characteristics

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 17 of 18© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is sub

Pagina 10 - Hardware STORE Cycle

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 18 of 18Document History PageDocument Title: CY14B101L 1-Mbit (128K x 8) nvSRAM Document Number

Pagina 11 - CY14B101LPRELIMINARY

Pagina 12 - during address transitions

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 2 of 18Pin ConfigurationsVCAPA16A14A12A7A6A5A4VCCA15HSBWEA13A8A9A11OEA10DQDQ76DQ5CEDQ4DQ3123456

Pagina 13

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 3 of 18Device OperationThe CY14B101L nvSRAM is made up of two functionalcomponents paired in th

Pagina 14

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 4 of 18Figure 1. AutoStore ModeHardware STORE OperationThe CY14B101L provides the HSB pin for c

Pagina 15

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 5 of 18Table 1. Mode SelectionCEWE OEA15 – A0 Mode IO PowerH X X X Not Selected Output High-Z S

Pagina 16

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 6 of 18Preventing AutoStoreDisable the AutoStore function by initiating an AutoStoreDisable seq

Pagina 17

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 7 of 18Maximum RatingsExceeding maximum ratings may shorten the device batterylife. These user

Pagina 18

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 8 of 18Capacitance [7] Parameter Description Test Conditions Max UnitCINInput Capacitance TA =

Pagina 19

CY14B101LPRELIMINARYDocument #: 001-06400 Rev. *E Page 9 of 18AC Switching Characteristics ParameterDescription25 ns part 35 ns part 45 ns partUnitMin